1. Technical Field
The present invention relates to a semiconductor storage device and a production method therefor.
2. Background Art
With a view to achieving higher integration and higher performance of an LSI, an SGT (Surrounding Gate Transistor) has been proposed which is a vertical transistor comprising a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see Patent Document 1: JP 2-188966A). In the SGT, a source, a gate and a drain are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor.
In cases where a DRAM is designed using an SGT, a memory cell array can be configured as a cross-point type, so that a cell size of 4F2 can be achieved, in theory. Thus, it is possible to drastically reduce a cell size, as compared with a conventional planar transistor-based DRAM having a cell size of 6F2 or 8F2. Therefore, an SGT-based DRAM (hereinafter referred to as “SGT-DRAM”) has great potential as a DRAM requiring higher integration as a top priority, and an embedded memory for a CPU requiring an increase in capacity of a cache memory, etc. An example of a conventional SGT-DRAM is disclosed in the Patent Document 1 and the following Patent Document 2. The conventional example will be described below.
An SGT-DRAM disclosed in the Patent Document 1 will be described based on FIGS. 60(a) and 60(b) which are a top plan view and a bird's-eye view thereof, respectively. Referring to the top plan view of FIG. 60(a), a pillar-shaped silicon layer 703 is formed on an intersection of a word line 701 and a bit line 702, and a selection transistor Qm7 is formed based on the pillar-shaped silicon layer. Further, a capacitance element Cm7 is formed on a top of the selection transistor. Thus, a cross-point memory cell, i.e., a memory cell located at the intersection of the bit line and the word line, is constructed. Referring to the bird's-eye view of FIG. 60(b), the bit line is comprised of an N+ diffusion layer 702, and the word line 701 is comprised of polysilicon. The pillar-shaped silicon layer 703 is fabricated by forming a contact hole to extend from a top to a bottom of the word line and then forming a gate dielectric film and a silicon film within the contact hole through epitaxial growth to make up the selection transistor Qm7. The capacitance element Cm7 is formed on the top of the selection transistor Qm7 to have the same structure as that of a capacitance element in a conventional stacked DRAM. In this SGT-DRAM, although a memory cell area is as small as 4F2, there is the following problem. The bit line comprised of the N+ diffusion layer 702 has a significantly high resistance, as compared with a bit line comprised of a metal film, such as a tungsten film, which is commonly used in conventional DRAMs having a cell size of 6F2 and 8F2. Particularly, as a prerequisite to achieving a cell size of 4F2 in this SGT-DRAM, it is necessary to form the bit line in a minimum fabrication size (F). Thus, along with progress of miniaturization, a DRAM operation speed becomes slower due to an increase in resistance of the bit line, to cause difficulty in achieving a DRAM operation speed required in the future.
The Patent Document 2 discloses an SGT-DRAM designed while taking into account the above problem. The SGT-DRAM disclosed in the Patent Document 2 will be described based on FIGS. 61(a) and 61(b) which are a top plan view and a sectional view thereof, respectively. Referring to the top plan view and the sectional view of FIGS. 61(a) and 61(b), in a DRAM cell, a capacitance contact 805 is laterally offset from a top of a pillar-shaped silicon layer 803. Thus, as compared with the DRAM cell in the Patent Document 1, a cell size is increased to about 8F2. However, a bit line 802 can be comprised of tungsten polyside (a laminated film of tungsten silicide and polysilicon) to have a lower resistance than that of the N+ diffusion layer, so that it is possible to suppress the problem of a reduction in DRAM operation speed due to an increase in resistance of a bit line in the Patent Document 1.
However, this SGT-DRAM has the following problem. The pillar-shaped silicon layer 803 is fabricated by forming a contact hole to extend from a top to a bottom of a gate electrode and then growing silicon from the tungsten polyside bit line within the contact hole, in the same manner as that in the Patent Document 1. The silicon is transformed into polysilicon through a heat treatment for forming a transistor, so that a large number of defects, such as grain boundaries, occur in the pillar-shaped silicon layer. DRAM production yield is extremely sensitive to junction leak caused by defects in a transistor. Thus, it is difficult to ensure sufficient production yield by the above production method. As above, although the SGT-DRAM disclosed in the Patent Document 2 is capable of lowering a resistance of a bit line, it would be hardly practicable due to difficulty in ensuring sufficient production yield.
As measures against an increase in resistance of a bit line as described above, it is contemplated to reduce the number of memory cells to be connected to one bit line, so as to shorten a length of the bit line. In existing planar transistor-based DRAMs, a bit line is comprised of a low-resistance metal film, and about 256 or 512 memory cells are generally connected to one bit line. For example, if the number of bit lines to be connected to one bit line can be reduced to about 32 or 64, it is possible to suppress the reduction in operation speed even if a high-resistance bit line is used. However, if the number of bit lines to be connected to one bit line is reduced to downsize a DRAM cell array, an extra area due to an increase in the number of peripheral circuits is increased to cause a significant increase in chip area.
Patent Document 1: JP 7-99311A
Patent Document 2: JP 7-244414A
In view of the above problems, as a prerequisite to practical realization of an SGT-DRAM, it is essential to achieve a memory cell capable of reducing a memory cell size to about 4F2, and lowering a resistance of a bit line, while ensuring sufficient production yield.
As means for lowering a resistance of a bit line, there are a first technique of using a low-resistance material for a bit line as in the Patent Document 2, and a second technique of backing a bit line with a low-resistance interconnection layer to provide a substantially low-resistance bit line. In the present invention, the second technique of backing a bit line with a low-resistance interconnection layer is employed as the means for lowering a resistance of a bit line.
The present invention provides a memory cell structure designed such that a high-resistance bit line comprised of a diffusion layer is backed with a relatively low-resistance interconnection line within a memory cell array to provide a substantially low-resistance bit line, while minimizing an increase in extra area.